Embedded dynamic random access memory (eDRAM) is a dynamic random access memory (DRAM) embedded in a logic circuit to function as a high density cache memory. The eDRAM provides comparable access time as static random access memory (SRAM) at a smaller device area per cell. Typically, eDRAM arrays are employed as an L2 level cache or L3 level cache in a processor to provide a high density memory in a processor core. Due to high performance and a compact size, eDRAM has become one of the most efficient means for continued performance of semiconductor logic circuits requiring embedded memory including processors and system-on-chip (SoC) devices.
Manufacturing of an eDRAM into a logic circuit in general introduces challenges in process integration, one of which is formation of shallow trench isolation that is compatible with the eDRAM and logic devices. While formation of the shallow trench isolation in a logic region may be effected by a standard complementary metal-oxide-semiconductor (CMOS) shallow trench isolation (STI) process, use of such a process introduces adverse or deleterious structural features in an embedded dynamic random access memory (eDRAM) region since the eDRAM region contains deep trenches comprising different materials than the logic region. Formation of such adverse or deleterious features is exacerbated if the substrate is a semiconductor-on-insulator (SOI) substrate.
Referring to FIG. 1, a prior art eDRAM structure formed in an SOI substrate 8′. The SOI substrate 8′ comprises a handle substrate 10′, a buried insulator layer 20′, and a top semiconductor layer 30′. The SOI substrate 8′ further comprises a pair of deep trenches, each of which comprise a node dielectric 50′ and a doped polysilicon fill 60′. The region of the handle substrate 10′ abutting the node dielectric 50′ is electrically doped to form a buried plate 6′.
The pair of deep trenches are formed by first providing an SOI substrate 8′ that does not contain any pattern, e.g., as provided by a commercial supplier of an SOI substrate 8′. A pad layer 40′ is formed directly on the top semiconductor layer 30′ by chemical vapor deposition (CVD). Optionally, a buffer layer (not shown), which is typically a thermal oxide layer, may be formed on top of the top semiconductor layer 30′ prior to formation of the pad layer 40′. A first photoresist (not shown) is applied over the pad layer 40′ and lithographically patterned to form openings over areas in which deep trenches are to be formed. The pattern is transferred into the pad layer 40′, the top semiconductor layer 30′, the buried insulator layer 20′, and the handle substrate 10′ to form the pair of deep trenches. A buried plate 6′ is formed outside the sidewalls of the deep trenches by diffusing dopants into the handle substrate 10′ from within the deep trenches. The node dielectric 50′ is formed on a sidewall of each of the pair of deep trenches, for example, by nitridation and/or deposition of silicon nitride. The pair of deep trenches is filled with doped polysilicon to form a pair of polysilicon trench fill regions 60′. Each of the polysilicon trench fill regions 60′ is recessed from a top surface of the pad layer 40′ to a first recess depth r1′ between a top surface of the buried insulator layer 20′ and a bottom surface of the buried insulator layer 20′. The node dielectric 50′ above the first recess depth r1′ of the polysilicon trench fill region 60′ is removed at this point. Additional doped polysilicon material is then deposited over the polysilicon trench fill regions 60′ to fill the pair of deep trenches, and then planarized and recessed from the top surface of the pad layer 40′ to a second recess depth r2′ which is between a top surface of the top semiconductor layer 30′ and a bottom surface of the top semiconductor layer 30′. By annexation of the additional doped polysilicon material, the polysilicon trench fill regions 60′ extends up to the second recess depth r2′.
Referring to FIG. 2, a second photoresist 90′ is applied over the pad layer 40′ and the polysilicon trench fill regions 60′. The second photoresist 90′ is lithographically patterned to form a first opening O1′ over a first shallow trench isolation area above the pair of deep trenches and a second opening O2′ over a second shallow trench isolation area outside the pair of deep trenches. The pattern of the first opening O1′ and the second opening O2′ is transferred into the top semiconductor layer 30′ and the polysilicon trench fill regions 60′.
Due to inhomogeneous composition between the top semiconductor layer 30′ and the polysilicon trench fill regions 60′, a non-uniform etch profile is obtained after the transfer of the pattern in the second photoresist 90′. Specifically, the buried insulator layer 20′ functions as a built-in etch-stop layer for a reactive ion etch that removes the semiconductor material of the top semiconductor layer 30′. However, the polysilicon trench fill regions 60′ does not contain any built-in etch-stop layer and the reactive ion etch continues beneath the level of the top surface of the buried insulator layer 20′. Further, the polysilicon trench fill regions 60′ comprises doped polysilicon which has a higher rate of etch than the semiconductor material of the top semiconductor layer 30′, which comprises single crystalline semiconductor material such as silicon and typically has a doping of low concentration, e.g., below 1.0×1017/cm3 in atomic concentration.
Thus, the combination of a higher etch rate of the polysilicon trench fill regions 60′ compared with the etch rate of the top semiconductor layer 30′ and the lack of a built-in etch-stop layer typically cause formation of divots in the polysilicon trench fill regions 60′ during the reactive ion etch. Further, in the case that the divots extend beneath the bottom surface of the buried insulator layer 20′, portions of the node dielectric 50′ may be damaged and/or thinned to form damaged node dielectric portions 50D, which may increase leakage of deep trench capacitors comprising the node dielectric 50′ and/or degrade reliability of the node dielectric 50′. Formation of such divots in the polysilicon trench fill regions 60′ thus causes deleterious effects on performance of the prior art eDRAM structure.
In view of the above, there exists a need for a semiconductor structure including an embedded dynamic random access memory (eDRAM) structure that is compatible with a semiconductor-on-insulator (SOI) substrate and is substantially free of deleterious structural features introduced during formation of shallow trench isolation, and methods of manufacturing the same.
Further, there exists a need for a semiconductor structure including a deep trench and a shallow trench isolation structure formed in an SOI substrate and is substantially free of deleterious structural features that may compromise performance or reliability of a deep trench capacitor formed therefrom.
Specifically, there exists a need for a semiconductor structure including a deep trench and a shallow trench isolation structure formed in an SOI substrate and is substantially free of damage to a node dielectric and divot formation within a fill material of the deep trench.